This invention relates generally to clock generation, and more particularly to generating a multiple phase clock.
Contemporary high performance computing main memory systems utilize high per-pin data rates to achieve high data bandwidth. Per-pin data rates can be increased by sending more data bits in a given clock period (e.g. a memory clock cycle). For example, a contemporary Fully Buffered DIMM (FBDIMM) transmits twelve data bits in the equivalent of a single memory clock cycle time. Further, some special purpose contemporary dynamic random access memories (DRAMs) transmit eight data bits in a single memory clock cycle time. To achieve this, multiple clock phases are required which must be developed by circuitry located in a device(s) within the main memory, within the memory controller, within the local clocking device, within the memory interface device (MID), and/or within other clock generation devices/circuitry. Other electronic devices and/or interfaces also require precise multiple clock phase generation, for example, some high-speed digital video disk (DVD) devices require sixty-three phases.
There are two conventional methods to generate multiple phases. The first is to divide the output of the voltage controlled oscillator (VCO). For example, dividing (e.g. via a toggle flip flop) a differential clock by two, then by two a second time, would generate eight phases. However, this requires the VCO circuitry to operate at a much higher frequency (four times in this case) and results in higher power requirements. The other method is to use a multiple stage ring oscillator. The latter case, however, decreases the output frequency inversely proportional to the number of phases. Therefore, it would be highly desirable to be able to generate multiple clock phases in a manner that provides for a minimum impact on the output frequency while consuming a relatively small amount of power.